Automated design systems are commonly used to layout and design integrated circuits and, in particular, to design back end of line (BEOL) interconnect structures. A design rule checker is employed by the design system to verify that the layout of the BEOL complies with mandated design rules. Design rule spacing constraints are imposed in BEOL interconnect structures on spacings for troughs in the dielectric material of different metallization levels (i.e., Mx-levels), which are filled by metal lines, and on spacings for vias in the dielectric material of different via layers (i.e., Vx-layers), which are filled by metal plugs that supply vertical interconnections between adjacent Mx-levels. The actual shapes for the troughs and vias are represented to the design rule checker as design shapes, such as rectangles and squares.
Design rules may be supplied to the design rule checker that limit the number and spacing of nearest neighbor via cuts or shapes in the Vx-layers. For example, a design rule may constrain the number of nearest neighbor via shapes that are permitted within a given center-to-center distance of any other arbitrary via shape. When actual via shapes are known, design rules on the number and spacing of nearest neighbor via shapes are relatively simple to implement when the integrated circuit is designed. However, the design rule checker may encounter difficulties if multiple discrete via shapes have been abstracted into a shape element known as a via obstruction (e.g., cores, technology library, via level abstraction, hierarchical objects). Specifically, the locations of the actual via shapes contained within the via obstruction are unknown to the design rule checker. In addition, the center of the via obstruction may not be the true center of a via shape within the via obstruction. Consequently, the design rule checker may not be able to accurately verify whether or not the relation between the via obstruction and other via shapes complies with the design rules.
Consequently, methods are needed that permit the design rule checker to comply with design rules on the spacing among nearest neighbor via shapes in Vx-layers when analyzing via shapes having the abstracted form of via obstructions.